The present invention deals with the data storage in digital signal processor chips having multiple processor-memory nodes. Conventional techniques would use a dual-port SRAM for a read and a write to be accomplished on a single clock cycle. Using a single port SRAM is normally much too restrictive and limits throughput by allowing only a read or a write in a given clock cycle. The bit cell size for a dual-port SRAM, however, is considerably larger typically four times as large as a cell for a single port SRAM. When a large SRAM is required, this is a significant silicon overhead.
One conventional technique which has been used to circumvent this limitation is to use a single port SRAM running at twice the frequency of the surrounding logic. This allows a simple time division multiplexing system to be used around the SRAM so that to the surrounding logic the SRAM appears dual ported. Each of the two-processor entities needing access to the SRAM appears to get it each cycle. In fact, one processor gets access in the first half of the cycle of the main clock and the second processor in the latter half. This works well at moderate clock speeds. However, if processor clock speed is itself aggressively high getting the SRAM to run at twice that speed is often not possible.